Model of an adder with parallel execution of micro-operations

  • O. N. Paulin Odessa National Polytechnic University, Ukraine
  • F. S. Shapo Odessa National Polytechnic University, Ukraine
  • N. I. Sinegub Odessa National Polytechnic University, Ukraine
Keywords: floating-point adders, timing diagrams, modeling, Active-HDL environment, Verilog language

Abstract

The functioning processes of different types of adders are analyzed through their modeling in Verilog within the Active-HDL environment. Timing diagrams were obtained, confirming the increased performance of adders with parallel execution of micro-operations compared to devices with sequential execution.

Published
2005-04-29
How to Cite
Paulin, O. N., Shapo, F. S., & Sinegub, N. I. (2005). Model of an adder with parallel execution of micro-operations. Technology and Design in Electronic Equipment, (2), 17-20. Retrieved from https://www.tkea.com.ua/index.php/journal/article/view/TKEA2005.2.17
Issue
No. 2 (2005): Tekhnologiya i konstruirovanie v elektronnoi apparature
Section
Articles

Copyright (c) 2005 Paulin O. N., Shapo F. S., Sinegub N. I.

Creative Commons License

This work is licensed under a Creative Commons Attribution 4.0 International License.