Architecture of digital signal’s processing units with the rebuildable structure

Abstract

The synthesis technique is developed for the computing system architecture with tunable structure with graph of information connections (GIC) affine transformations which assumes additional equipment of initial computing system (CS) with the appropriate switching system implementing, depending on character of GIC change, one of the methods of block reorganization providing effective implementation of CS in wide range of GIC parameters change. The received estimations of hardware expenses for various methods of reorganization allow to define efficiency of CS implementation for each specific case.