Testable binary adder circuit based on a 16‑bit section group

Abstract

A testable functional‑logical circuit of a binary adder based on a 16‑bit group of 4‑bit sections is considered. The design provides simultaneous carry propagation within each section and section group, and sequential carry propagation between groups. The circuit was developed within the concept of “constant” testability of digital circuits. The proposed scheme features a verifying test of length 11 with respect to all its single constant faults.