Design of adders in the Active-HDL environment with preliminary analysis of characteristics

  • O. N. Paulin Odessa National Polytechnic University, Ukraine
  • F. S. Shapo Odessa National Polytechnic University, Ukraine
  • N. I. Sinegub Odessa National Polytechnic University, Ukraine
  • S. O. Poleschuk Odessa National Polytechnic University, Ukraine
Keywords: Verilog language, Active-HDL environment, digital device modeling, floating-point adders, alignment difference, hardware cost, timing diagrams

Abstract

A series of original floating-point adders has been designed. The results of analyzing their operation, based on functional models written in Verilog HDL and simulated in the Active-HDL environment, confirm that preliminary determination of l least significant bits of the exponent difference (alignment difference) reduces hardware cost while decreasing performance as l increases.

Published
2007-06-29
How to Cite
Paulin, O. N., Shapo, F. S., Sinegub, N. I., & Poleschuk, S. O. (2007). Design of adders in the Active-HDL environment with preliminary analysis of characteristics. Technology and Design in Electronic Equipment, (3), 9-14. Retrieved from https://www.tkea.com.ua/index.php/journal/article/view/TKEA2007.3.09
Issue
No. 3 (2007): Tekhnologiya i konstruirovanie v elektronnoi apparature
Section
Articles

Copyright (c) 2007 Paulin O. N., Shapo F. S., Sinegub N. I., Poleschuk S. O.

Creative Commons License

This work is licensed under a Creative Commons Attribution 4.0 International License.