Optimization of the fabrication process of a high-voltage lateral p-channel MOS transistor

Abstract

Simulation of semiconductor structures provides an opportunity to reduce manufacturing costs and optimize the parameters of integrated circuit elements and devices. To design integrated circuits with specified properties, it is necessary to obtain the required electrical characteristics of the circuit elements. This paper presents the results of optimization simulation of the technological route and electrical characteristics of a high-voltage lateral p-channel MOS transistor, which has a threshold voltage of 0.8–1.8 V, a drain-source breakdown voltage above 80 V, and an on-state drain current exceeding 0.5 mA at a gate voltage of 5 V. The simulated technological route of the PMOS transistor includes n-type epitaxial film growth on a p-type substrate, polysilicon gate formation, p-type drain region formation, p+ source and drain region formation, intermediate oxide deposition, and metal deposition. The transistor’s I–V characteristics were obtained from calculations considering variations in epitaxial film specific resistance (ρv) and gate oxide thickness (d). The tendencies of threshold voltage changes of the PMOS transistor were identified as a result of simulation in accordance with ρv and d variations. Experimental samples were fabricated in epitaxial films with different values of ρv and d. Comparison of experimental data with simulation results allowed determination of the most acceptable values of ρv and d (taking into account production conditions), ensuring the required threshold voltage of the analyzed transistor.