Implementation of high-speed digital filter elements on FPGAs

  • V. P. Malahov Odessa National Polytechnic University, Ukraine
  • V. S. Sitnikov Odessa National Polytechnic University, Ukraine
  • P. V. Yadvichuk Odessa National Polytechnic University, Ukraine
Keywords: FPGA, non-recursive digital filter, multi-bit shift register, adder, vector binary multiplier

Abstract

This paper addresses the problem of implementing a high-speed non-recursive digital filter on a FPGA. Methods for constructing high-speed filter elements are investigated: a multi-bit shift register, a vector binary multiplier, and a vector binary adder. The paper provides examples of the description of these elements in the VHDL description language.

Published
2004-08-30
How to Cite
Malahov, V. P., Sitnikov, V. S., & Yadvichuk, P. V. (2004). Implementation of high-speed digital filter elements on FPGAs. Technology and Design in Electronic Equipment, (4), 3-8. Retrieved from https://www.tkea.com.ua/index.php/journal/article/view/TKEA2004.4.03
Issue
No. 4 (2004): Tekhnologiya i konstruirovanie v elektronnoi apparature
Section
Articles

Copyright (c) 2004 Malahov V. P., Sitnikov V. S., Yadvichuk P. V.

Creative Commons License

This work is licensed under a Creative Commons Attribution 4.0 International License.